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Author
Age
*
Another block of spelling fixes
Larry Doolittle
2015-08-14
*
Fixed trailing whitespaces
Clifford Wolf
2015-07-02
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Various fixes for memories with offsets
Clifford Wolf
2015-02-14
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Added $meminit support to "memory" command
Clifford Wolf
2015-02-14
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Added $meminit test case
Clifford Wolf
2015-02-14
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improvements in muxtree/select_leaves test
Clifford Wolf
2015-01-18
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Improvements in opt_muxtree
Clifford Wolf
2015-01-18
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Added support for task and function args in parentheses
Clifford Wolf
2014-10-27
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Added multi-dim memory test (requires iverilog git head)
Clifford Wolf
2014-08-12
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Improved scope resolution of local regs in Verilog+AST frontend
Clifford Wolf
2014-08-05
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Fixed AST handling of variables declared inside a functions main block
Clifford Wolf
2014-08-05
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Added "make -j{N}" support to "make test"
Clifford Wolf
2014-07-30
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Added support for "upto" wires to Verilog front- and back-end
Clifford Wolf
2014-07-28
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Renamed some of the test cases in tests/simple to avoid name collisions
Clifford Wolf
2014-07-25
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Implemented dynamic bit-/part-select for memory writes
Clifford Wolf
2014-07-17
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Added support for bit/part select to mem2reg rewriter
Clifford Wolf
2014-07-17
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Added support for constant bit- or part-select for memory writes
Clifford Wolf
2014-07-17
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Added note to "make test": use git checkout of iverilog
Clifford Wolf
2014-07-16
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fixed parsing of constant with comment between size and value
Clifford Wolf
2014-07-02
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Fixed handling of mixed real/int ternary expressions
Clifford Wolf
2014-06-25
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Little steps in realmath test bench
Clifford Wolf
2014-06-21
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Added test case for AstNode::MEM2REG_FL_CMPLX_LHS
Clifford Wolf
2014-06-17
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Removed long running tests from tests/simple/realexpr.v (replaced by tests/re...
Clifford Wolf
2014-06-15
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Added tests/realmath to "make test"
Clifford Wolf
2014-06-15
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Added support for math functions
Clifford Wolf
2014-06-14
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Added realexpr.v test case
Clifford Wolf
2014-06-14
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added tests for new verilog features
Clifford Wolf
2014-06-07
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Added tests/simple/repwhile.v
Clifford Wolf
2014-06-06
*
Progress in Verific bindings
Clifford Wolf
2014-03-17
*
Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)
Clifford Wolf
2014-02-03
*
Bugfix in name resolution with generate blocks
Clifford Wolf
2014-01-30
*
Added correct handling of $memwr priority
Clifford Wolf
2014-01-03
*
Added proper === and !== support in constant expressions
Clifford Wolf
2013-12-27
*
Added multiplier test case from eda playground
Clifford Wolf
2013-12-18
*
Added elsif preproc support
Clifford Wolf
2013-12-18
*
Added support for macro arguments
Clifford Wolf
2013-12-18
*
Various improvements in support for generate statements
Clifford Wolf
2013-12-04
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Replaced RTLIL::Const::str with generic decoder method
Clifford Wolf
2013-12-04
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Fix in sincos testbench gen
Clifford Wolf
2013-12-04
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Added sincos test case
Clifford Wolf
2013-12-04
*
Implemented correct handling of signed module parameters
Clifford Wolf
2013-11-24
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Added modelsim support to autotest
Clifford Wolf
2013-11-24
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Another name resolution bugfix for generate blocks
Clifford Wolf
2013-11-20
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Implemented indexed part selects
Clifford Wolf
2013-11-20
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Implemented part/bit select on memory read
Clifford Wolf
2013-11-20
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Added additional mem2reg testcase
Clifford Wolf
2013-11-18
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Fixed parsing of default cases when not last case
Clifford Wolf
2013-11-18
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Fixed handling of power operator
Clifford Wolf
2013-11-07
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Behavior should be identical now to rev. 0b4a64ac6adbd6 (next: testing before...
Clifford Wolf
2013-11-02
*
Various ast changes for early expression width detection (prep for constfold ...
Clifford Wolf
2013-11-02
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