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* Implemented recursive techmapClifford Wolf2014-08-03
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* Implemented simplemap support for "techmap -extern"Clifford Wolf2014-08-02
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* Bugfix in "techmap -extern"Clifford Wolf2014-08-02
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* No implicit conversion from IdString to anything elseClifford Wolf2014-08-02
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* More bugfixes related to new RTLIL::IdStringClifford Wolf2014-08-02
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* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-02
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* Replaced sha1 implementationClifford Wolf2014-08-01
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* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-31
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* Added module->design and cell->module, wire->module pointersClifford Wolf2014-07-31
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* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-31
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* Renamed "stdcells.v" to "techmap.v"Clifford Wolf2014-07-31
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* Added "techmap -assert"Clifford Wolf2014-07-31
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* Added techmap CONSTMAP featureClifford Wolf2014-07-30
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* Added "techmap -map %{design-name}"Clifford Wolf2014-07-29
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* Using log_assert() instead of assert()Clifford Wolf2014-07-28
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* Added techmap -externClifford Wolf2014-07-27
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* Added topological sorting to techmapClifford Wolf2014-07-27
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* Using new obj iterator API in a few placesClifford Wolf2014-07-27
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* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-27
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* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-27
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* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-27
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* Changed more code to the new RTLIL::Wire constructorsClifford Wolf2014-07-26
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* More RTLIL::Cell API usage cleanupsClifford Wolf2014-07-26
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* Manual fixes for new cell connections APIClifford Wolf2014-07-26
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* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
| | | | | | | | | git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;'
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
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* Added copy-constructor-like module->addCell(name, other) methodClifford Wolf2014-07-26
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* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-25
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* Added "make SMALL=1"Clifford Wolf2014-07-24
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* Added "make PRETTY=1"Clifford Wolf2014-07-24
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* Removed RTLIL::SigSpec::expand() methodClifford Wolf2014-07-23
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* Fixed all users of SigSpec::chunks_rw() and removed itClifford Wolf2014-07-23
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* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3Clifford Wolf2014-07-23
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* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3Clifford Wolf2014-07-23
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* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, ↵Clifford Wolf2014-07-22
| | | | created interim RTLIL::SigSpec::chunks_rw()
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-22
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* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22
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* Replaced depricated NEW_WIRE macro with module->addWire() callsClifford Wolf2014-07-21
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* Removed deprecated module->new_wire()Clifford Wolf2014-07-21
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* Added call_on_selection() and call_on_module() APIClifford Wolf2014-07-20
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* Added support for "blackbox" attribute to iopadmapClifford Wolf2014-07-17
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* Added support for "blackbox" attribute to flatten/techmapClifford Wolf2014-07-17
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* be more verbose when techmap yielded processesJohann Glaser2014-05-26
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* Merged OSX fixes from Siesh1oo with some modificationsClifford Wolf2014-03-13
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* - kernel/register.h, kernel/driver.cc: refactor ↵Siesh1oo2014-03-12
| | | | | | | rewrite_yosys_exe()/get_share_file_name() to portable proc_self_dirname()/proc_share_dirname(). This refactoring improves robustness and allows OSX support with only 7 new lines of code, and easy extension for other systems. - passes/abc/abc.cc, passes/cmds/show.cc, passes/techmap/techmap.cc: use new, refactored semantics.
* OSX compatible creation of stdcells.inc, using code from ↵Clifford Wolf2014-03-11
| | | | | | github.com/Siesh1oo/yosys (see https://github.com/cliffordwolf/yosys/pull/28)
* Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosysClifford Wolf2014-03-11
| | | | (see https://github.com/cliffordwolf/yosys/pull/28)
* Fixed dumping of timing() { .. } block in libparseClifford Wolf2014-03-09
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* Added techmap -max_iter optionClifford Wolf2014-03-06
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* Added _TECHMAP_REPLACE_ feature to techmapClifford Wolf2014-02-20
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