yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
*	Corrected spelling mistakes found by lintian	Ruben Undheim	2014-09-06
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*	Added module->ports	Clifford Wolf	2014-08-14
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*	More bugfixes related to new RTLIL::IdString	Clifford Wolf	2014-08-02
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*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02
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*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31
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*	Added module->design and cell->module, wire->module pointers	Clifford Wolf	2014-07-31
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*	Allow "hierarchy -generate" for $__ cells	Clifford Wolf	2014-07-29
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*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28
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*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27
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*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27
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*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27
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*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26
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*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26
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*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26
\| \| \| \| \| \| \| \| \|	git grep -l 'connections_' \| xargs sed -i -r -e ' s/(->\|\.)connections_\["([^"])"\] = (.);/\1set("\2", \3);/g; s/(->\|\.)connections_\["([^"])"\]/\1get("\2")/g; s/(->\|\.)connections_.at$"([^"])"$/\1get("\2")/g; s/(->\|\.)connections_.push_back/\1connect/g; s/(->\|\.)connections_/\1connections()/g;'
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26
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*	Added copy-constructor-like module->addCell(name, other) method	Clifford Wolf	2014-07-26
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*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25
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*	Fixed all users of SigSpec::chunks_rw() and removed it	Clifford Wolf	2014-07-23
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*	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, ↵	Clifford Wolf	2014-07-22
\| \| \| \|	created interim RTLIL::SigSpec::chunks_rw()
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22
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*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22
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*	Added call_on_selection() and call_on_module() API	Clifford Wolf	2014-07-20
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*	fixed cell array handling of positional arguments	Clifford Wolf	2014-06-07
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*	Add support for cell arrays	Clifford Wolf	2014-06-07
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*	Implemented read_verilog -defer	Clifford Wolf	2014-02-13
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*	Moved some passes to other source directories	Clifford Wolf	2014-02-08
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*	Added hierarchy -purge_lib option	Clifford Wolf	2014-02-04
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*	Include unistd.h in passes/hierarchy/hierarchy.cc (required for access(3))	Martin Schmölzer	2014-01-14
\| \| \| \| \| \|	This fixes compilation errors on Arch Linux. Signed-off-by: Martin Schmölzer <martin.schmoelzer@student.tuwien.ac.at>
*	Added hierarchy -libdir option	Clifford Wolf	2014-01-14
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*	Replaced signed_parameters API with CONST_FLAG_SIGNED	Clifford Wolf	2013-12-04
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*	Remove auto_wire framework (smarter than the verilog standard)	Clifford Wolf	2013-11-24
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*	Implemented correct handling of signed module parameters	Clifford Wolf	2013-11-24
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*	Added "top" attribute to mark top module in hierarchy	Clifford Wolf	2013-11-24
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*	Renamed "placeholder" to "blackbox"	Clifford Wolf	2013-11-22
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*	Added resolution of positional arguments to hierarchy pass	Clifford Wolf	2013-11-03
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*	Fixed handling of boolean attributes (passes)	Clifford Wolf	2013-10-24
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*	Improved log messages generated by hierarchy pass	Clifford Wolf	2013-05-26
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*	Fixed hierarchy pass for hierarchies of parametric modules	Clifford Wolf	2013-04-26
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*	Implemented proper handling of stub placeholder modules	Clifford Wolf	2013-03-28
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*	Collect parameters in hierarchy -generate (and do nothing with them)	Clifford Wolf	2013-03-26
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*	Added hierarchy -generate command for generating skeletton modules	Clifford Wolf	2013-03-25
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*	Implemented general handler for selection arguments	Clifford Wolf	2013-03-03
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*	Added online help for "show" and "hierarchy" commands	Clifford Wolf	2013-02-28
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*	initial import	Clifford Wolf	2013-01-05